Texas Instruments SN74AUP2G34 Low-Power Dual Buffer Gate
Texas Instruments SN74AUP2G34 Low-Power Dual Buffer Gate performs the Boolean function Y = A in positive logic. The AUP family ensures very low static and dynamic power consumption across the entire VCC range of 0.8V to 3.6V, resulting in increased battery life. This product also maintains excellent signal integrity.
NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. The Texas Instruments SN74AUP2G34 is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when powered down.
Features
- Available in the Texas Instruments NanoStar package
- Low static-power consumption of ICC = 0.9µA (max.)
- Low dynamic-power consumption of Cpd = 4.3pF (typ.) at 3.3V
- Low input capacitance of Ci = 1.5pF (typ.)
- Low noise with overshoot and undershoot of < 10% of VCC
- Ioff supports partial-power-down mode operation
- Wide operating VCC range of 0.8V to 3.6V
- Optimized for 3.3V operation
- 3.6V I/O tolerant to support mixed-mode signal operation
- tpd = 4.3ns (max.) at 3.3V
- Suitable for point-to-point applications
- Latch-up performance exceeds 100mA per JESD 78, Class II
- ESD performance tested per JESD 22
- 2000V human-body model (A114-B, Class II)
- 1000V charged-device model (C101)
Applications
- Battery-powered applications
- Mixed-mode applications
- Partial-power-down mode
Logic Diagram (Positive Logic)
Development Tool
Texas Instruments 5-8-LOGIC-EVM Evaluation Module
Developed to support leaded Logic devices in the DBV, DCK, DCT, DCU, and DRL packages.
Published: 2025-02-14
| Updated: 2025-03-07