Texas Instruments TMS320DM643 Fixed-Point Digital Signal Processor

This device delivers up to 4800 million instructions per second (MIPS) at a clock rate of 600MHz. The TMS320DM643 device offers cost-effective solutions for high-performance DSP programming challenges. The TMS320DM643 DSP possesses the numerical capability of array processors and the operational flexibility of high-speed controllers. The C64x DSP core processor has 64 general-purpose registers with 32-bit word length and eight highly independent functional units (six arithmetic logic units (ALUs) and two multipliers for a 32-bit result) with VelociTI.2 extensions.

The TMS320DM643 has a powerful and diverse set of peripherals and uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 128Kbit direct-mapped cache, and the Level 1 data cache (L1D) is a 128Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 2Mbit memory space shared between data and program spaces. L2 memory can be configured as mapped memory, a cache, or a combination of the two.

The peripheral set includes: a 10/100 Mb/s Ethernet MAC (EMAC); two configurable video ports; a management data input/output (MDIO) module; one multichannel buffered audio serial port (McASP0); a VCXO interpolated control port (VIC); an inter-integrated circuit (I²C) Bus module; one multichannel buffered serial port (McBSP); a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); three 32-bit general-purpose timers; a 16-pin general-purpose input/output port (GP0) with programmable interrupt/event generation modes; and a 64-bit glueless external memory interface (EMIFA), which is capable of interfacing to synchronous and peripherals and asynchronous memories.

The Texas Instruments TMS320DM643 has two configurable video port peripherals (VP1 and VP2). These video port peripherals provide a glueless interface to common video encoder and decoder devices. The TMS320DM643 video port peripherals support multiple video standards (e.g., CCIR601, ITU-BT.656, BT.1120, SMPTE 125M, 260M, 274M, and 296M) and resolutions. These two video port peripherals can support either video capture and/or video display modes and are configurable. Each video port consists of two channels - A and B, with a 5120-byte capture/display buffer that is splittable between the two channels.

The McASP0 port supports one receive and one transmit clock zone, with eight serial data pins that can be individually allocated to either zone. The serial port supports time-division multiplexing on each pin from 2 to 32 time slots. The TMS320DM643 has sufficient bandwidth to support all 8 serial data pins transmitting a 192kHz stereo signal. Serial data in each zone may be received and formatted in a multitude of variations on the Philips Inter-IC Sound (I²S) format and transmitted on multiple serial data pins simultaneously. In addition, the McASP0 transmitter may be programmed to output multiple S/PDIF, AES-3, IEC60958, and CP-430-encoded data channels simultaneously, with a single RAM containing the full implementation of the channel status fields and user data.

The Ethernet Media Access Controller (EMAC) provides an efficient interface between the TMS320DM643 DSP core processor and the network. The TMS320DM643 EMAC supports both 10Base-T and 100Base-TX, or 10Mbps and 100Mbps, in either half- or full-duplex, with quality of service (QOS) support and hardware flow control. The TMS320DM643 EMAC uses a custom interface to the DSP core, enabling efficient data transmission and reception.

The management data input/output (MDIO) module continuously polls all 32 MDIO addresses to enumerate all PHY devices in the system. Once the DSP has selected a PHY candidate, the MDIO module transparently monitors its link state by reading the PHY status register. Link change events are stored in the MDIO module and can optionally interrupt the DSP, allowing the DSP to poll the device's link status without continuously performing costly MDIO accesses.

The I2C0 port on the TMS320DM643 enables the DSP to control peripheral devices and communicate with a host processor easily. In addition, the standard multichannel buffered serial port (McBSP) may be used to communicate with serial peripheral interface (SPI) mode peripheral devices.