NXP LS1022A Series Microprocessors - MPU

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Description Datasheet Availability Pricing (EUR) Filter the results in the table by unit price based on your quantity.
Qty. RoHS ECAD Model Core
Number of Cores
Data Bus Width
Maximum Clock Frequency
Package/Case
L1 Cache Instruction Memory
L1 Cache Data Memory
Operating Supply Voltage
Series
Mounting Style
Minimum Operating Temperature
Maximum Operating Temperature
Number of I/Os
Packaging
NXP Semiconductors Microprocessors - MPU Layerscape 32-bit Arm Cortex-A7, Dual-core, 600MHz, 0 to 105C, Security enabled
Datasheet
Non-Stocked Lead-Time 52 Weeks
Min.: 84
Mult.: 84
ARM Cortex A7 2 Core 32 bit 600 MHz FCPBGA-525 32 kB 32 kB 1 V LS1022A SMD/SMT 0 C + 105 C 109 I/O Tray
NXP Semiconductors Microprocessors - MPU Layerscape 32-bit Arm Cortex-A7, Dual-core, 600MHz, 0 to 105C, Security disabled
Datasheet
Non-Stocked Lead-Time 52 Weeks
Min.: 84
Mult.: 84

ARM Cortex A7 2 Core 32 bit 600 MHz FCPBGA-525 32 kB 32 kB 1 V LS1022A SMD/SMT 0 C + 105 C 109 I/O Tray
NXP Semiconductors Microprocessors - MPU Layerscape 32-bit Arm Cortex-A7, Dual-core, 600MHz, -40 to 105C, Security enabled
Datasheet
Non-Stocked Lead-Time 52 Weeks
Min.: 1
Mult.: 1

ARM Cortex A7 2 Core 32 bit 600 MHz FCPBGA-525 32 kB 32 kB 1 V LS1022A SMD/SMT - 40 C + 105 C 109 I/O Tray
NXP Semiconductors Microprocessors - MPU Layerscape 32-bit Arm Cortex-A7, Dual-core, 600MHz, -40 to 105C, Security disabled
Datasheet
Non-Stocked Lead-Time 52 Weeks
Min.: 84
Mult.: 84

ARM Cortex A7 2 Core 32 bit 600 MHz FCPBGA-525 32 kB 32 kB 1 V LS1022A SMD/SMT - 40 C + 105 C 109 I/O Tray