74AVC1T45DW-7

Diodes Incorporated
621-74AVC1T45DW-7
74AVC1T45DW-7

Mfr.:

Description:
Translation - Voltage Levels Logic AVC 1G Translator

ECAD Model:
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In Stock: 1,447

Stock:
1,447 Can Dispatch Immediately
Factory Lead Time:
40 Weeks Estimated factory production time for quantities greater than shown.
Minimum: 1   Multiples: 1
Unit Price:
€-.--
Ext. Price:
€-.--
Est. Tariff:
Packaging:
Full Reel (Order in multiples of 3000)

Pricing (EUR)

Qty. Unit Price
Ext. Price
Cut Tape / MouseReel™
€0.301 €0.30
€0.188 €1.88
€0.162 €4.05
€0.127 €12.70
€0.11 €27.50
€0.097 €48.50
€0.089 €89.00
Full Reel (Order in multiples of 3000)
€0.076 €228.00
€0.064 €384.00
† A MouseReel™ fee of €5.00 will be added and calculated in your basket. All MouseReel™ orders are non-cancellable and non-returnable.

Product Attribute Attribute Value Select Attribute
Diodes Incorporated
Product Category: Translation - Voltage Levels
RoHS:  
Level Shifter
Translator
SOT-363-6
3.6 V
1.2 V
74AVC1T45
2.8 ns
- 40 C
+ 85 C
SMD/SMT
Reel
Cut Tape
MouseReel
Brand: Diodes Incorporated
Logic Family: AVC
Number of Channels: 1 Channel
Operating Supply Current: 20 uA
Output Type: 3-State
Product Type: Translation - Voltage Levels
Factory Pack Quantity: 3000
Subcategory: Logic ICs
Unit Weight: 7.500 mg
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TARIC:
8542399000
CNHTS:
8542399000
CAHTS:
8542390000
USHTS:
8542390090
MXHTS:
8542399999
ECCN:
EAR99

74AVC1T45 Dual Supply Transceiver

Diodes Inc. 74AVC1T45 Transceiver is a single bit, dual supply device with 3-state outputs, suitable for transmitting a single logic bit across different voltage domains. The A input/output pin of the 74AVC1T45 is designed to track VCCA while the B input/output tracks VCCB. This arrangement allows for universal low-voltage translation between any voltages from 1.2V to 3.6V. The Direction pin (DIR) controls the direction of the 74AVC1T45 Transceiver that has logic threshold voltages related to VCCA. When a high logic level is applied to DIR the A pin becomes an input and the B pin becomes the output. Conversely, the roles of A and B are reversed when DIR is asserted low.